pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 59

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
6.4
Table 6-7. Assertion of P_SERR_L for Data Parity Errors
SYSTEM ERROR (SERR_L) REPORTING
PI7C8150B uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 6.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150B asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150B
also sets the received system error bit in the secondary status register.
PI7C8150B also conditionally asserts P_SERR_L for any of the following reasons:
2
3
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
P_SERR_L
1 (de-asserted)
1
1
1
1
0
0
1
1
1
1
1
X = don’t care
2
3
(asserted)
For PI7C8150B to assert P_SERR_L for any reason, the SERR_L enable bit must be
set in the command register.
Whenever PI7C8150B asserts P_SERR_L, PI7C8150B must also set the signaled
system error bit in the status register.
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
received)
PI7C8150B did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
The SERR_L enable bit must be set in the command register.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
24
(default) attempts to deliver (2
Primary
Secondary
Secondary
Secondary
Primary
Secondary
Primary
Primary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
APRIL 2006 – Revision 2.02
24
target retries
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / x
Secondary Parity
Error Response
Primary /
PI7C8150B
Bits