pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 7

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
13
14
13.1
13.2
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1.17
14.1.18
14.1.19
14.1.20
14.1.21
OFFSET 28h ....................................................................................................................................... 81
14.1.22
OFFSET 2Ch....................................................................................................................................... 81
14.1.23
14.1.24
14.1.25
14.1.26
14.1.27
14.1.28
14.1.29
14.1.30
14.1.31
14.1.32
14.1.33
4Ch
14.1.34
14.1.35
14.1.36
14.1.37
58h
14.1.38
14.1.39
14.1.40
14.1.41
14.1.42
14.1.43
SUPPORTED COMMANDS......................................................................................................... 72
CONFIGURATION REGISTERS................................................................................................ 74
PRIMARY INTERFACE ............................................................................................................. 72
SECONDARY INTERFACE....................................................................................................... 73
CONFIGURATION REGISTER ................................................................................................. 74
VENDOR ID REGISTER – OFFSET 00h......................................................................... 75
DEVICE ID REGISTER – OFFSET 00h .......................................................................... 75
COMMAND REGISTER – OFFSET 04h.......................................................................... 75
STATUS REGISTER – OFFSET 04h ................................................................................ 76
REVISION ID REGISTER – OFFSET 08h ...................................................................... 77
CLASS CODE REGISTER – OFFSET 08h....................................................................... 77
CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 77
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 77
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 77
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 78
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 78
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 78
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 78
I/O BASE REGISTER – OFFSET 1Ch.......................................................................... 78
I/O LIMIT REGISTER – OFFSET 1Ch ........................................................................ 79
SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 79
MEMORY BASE REGISTER – OFFSET 20h .............................................................. 80
MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 80
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ................................ 80
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ............................ 80
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 81
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 81
ECP POINTER REGISTER – OFFSET 34h................................................................. 81
INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 81
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 82
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 82
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 83
ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 84
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 85
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ............................... 85
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h ........................ 86
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h....................... 86
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 87
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 88
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 88
P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 89
PORT OPTION REGISTER – OFFSET 74h ................................................................ 90
RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 91
.......................................................................................................................................... 86
.......................................................................................................................................... 87
.......................................................................................................................................... 87
Page 7 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B