pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 36

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.8.2
3.8.3
3.8.3.1
MASTER ABORT RECEIVED BY PI7C8150B
If the initiator initiates a transaction on the target bus and does not detect DEVSEL_L
returned by the target within five clock cycles of the assertion of FRAME_L, PI7C8150B
terminates the transaction with a master abort. This sets the received-master-abort bit in the
status register corresponding to the target bus.
For delayed read and write transactions, PI7C8150B is able to reflect the master abort
condition back to the initiator. When PI7C8150B detects a master abort in response to a
delayed transaction, and when the initiator repeats the transaction, PI7C8150B does not
respond to the transaction with DEVSEL_L, which induces the master abort condition back
to the initiator. The transaction is then removed from the delayed transaction queue. When
a master abort is received in response to a posted write transaction, PI7C8150B discards
the posted write data and makes no more attempts to deliver the data. PI7C8150B sets the
received-master-abort bit in the status register when the master abort is received on the
primary bus, or it sets the received master abort bit in the secondary status register when
the master abort is received on the secondary interface. When master abort is detected in
posted write transaction with both master-abort-mode bit (bit 5 of bridge control register)
and the SERR_L enable bit (bit 8 of command register for secondary bus) are set,
PI7C8150B asserts P_SERR_L if the master-abort-on-posted-write is not set. The master-
abort-on-posted-write bit is bit 4 of the P_SERR_L event disable register (offset 64h).
Note: When PI7C8150B performs a Type 1 to special cycle conversion, a master abort is
the expected termination for the special cycle on the target bus. In this case, the master
abort received bit is not set, and the Type 1 configuration transaction is disconnected after
the first data phase.
TARGET TERMINATION RECEIVED BY PI7C8150B
When PI7C8150B initiates a transaction on the target bus and the target responds with
DEVSEL_L, the target can end the transaction with one of the following types of
termination:
PI7C8150B handles these terminations in different ways, depending on the type of
transaction being performed.
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8150B initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 3-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C8150B repeats a delayed write transaction until one of the following conditions is met:
Normal termination (upon de-assertion of FRAME_L)
Target retry
Target disconnect
Target abort
PI7C8150B completes at least one data transfer.
PI7C8150B receives a master abort.
PI7C8150B receives a target abort.
Page 36 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B