mt45w8mw16bgx Micron Semiconductor Products, mt45w8mw16bgx Datasheet - Page 16

• Manufacturer Part Number: mt45w8mw16bgx
• Description: 128mb 8 Meg X 16 Async/page/burst Cellularram 1.5 Async/ Page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

LB#/UB# Operation
Figure 11:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
DQ[15:0]
LB#/UB#
A[22:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Refresh Collision During Variable-Latency READ Operation
Additional WAIT states inserted to allow refresh completion.
Notes:
High-Z
Address
Valid
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE
operations, any disabled bytes will not be transferred to the RAM array and the internal
value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
LB# and UB# must be LOW during READ cycles.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
1. Non-default BCR settings for refresh collision during variable-latency READ operation:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
D0
D1
D2
Undefined
©2004 Micron Technology, Inc. All rights reserved.
D3
Don’t Care