mt45w8mw16bgx Micron Semiconductor Products, mt45w8mw16bgx Datasheet - Page 10

• Manufacturer Part Number: mt45w8mw16bgx
• Description: 128mb 8 Meg X 16 Async/page/burst Cellularram 1.5 Async/ Page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Power-Up Initialization Timing
In general, the MT45W8MW16BGX device is a high-density alternative to SRAM and
pseudo-SRAM products, popular in low-power, portable applications.
The MT45W8MW16BGX contains a 134,217,728-bit DRAM core, organized as 8,388,608
addresses by 16 bits. The device implements the same high-speed bus interface found
on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-
chronous read protocol.
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their default
settings. (See Figure 18 on page 24 and Figure 24 on page 31.) V
applied simultaneously. When they reach a stable level at or above 1.7V, the device will
require 150µs to complete its self-initialization process. During the initialization period,
CE# should remain HIGH. When initialization is complete, the device is ready for
normal operation.
V
The MT45W8MW16BGX CellularRAM product incorporates a burst mode interface
found on Flash products targeting low-power, wireless applications. This bus interface
supports asynchronous, page mode, and burst mode read and write transfers. The
specific interface supported is defined by the value loaded into the BCR. Page mode is
controlled by the refresh configuration register (RCR[7]).
CellularRAM 1.5 products power up in the asynchronous operating mode. This mode
uses the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ opera-
tions (Figure 5 on page 11) are initiated by bringing CE#, OE#, and LB#/UB# LOW while
keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed. WRITE operations (see Figure 6 on page 11) occur when CE#, WE#,
and LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is
a “Don't Care,” and WE# will override OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page
mode disabled) can either use the ADV# input to latch the address, or ADV# can be
driven LOW during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW. WAIT will be
driven while the device is enabled and its state should be ignored. WE# LOW time must
be limited to
CC
V
CC
Q
V
CC
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
= 1.7V
t
CEM.
Device initialization
t PU >
150µs
10
Device ready for
normal operation
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
©2004 Micron Technology, Inc. All rights reserved.
CC
and V
CC
Q must be