mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 83

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 46:
Figure 47:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Bank address
Bank address
Command
Command
Address
Address
CK#
CK#
CK
CK
Bank a
Bank x
Row
ACT
Row
T0
ACT
Example: Meeting
Multi-Bank Activate Restriction
T0
Notes:
t RRD (MIN)
READ
Bank a
Col
T1
NOP
T1
A subsequent ACTIVATE command to a different row in the same bank can only be
issued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVATE commands to different banks is defined by
t
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement:
requires no more than four ACTIVATE commands may be issued in any given
(MIN) period, as shown in Figure 47.
1. DDR2-533 (-37E, x4 or x8),
RRD.
t RRD
t
FAW (MIN) = 37.5ns.
Bank b
Row
ACT
T2
NOP
T2
t
RRD (MIN) and
READ
Bank b
Col
T3
Bank y
Row
ACT
T3
Bank c
Row
ACT
T4
t
t
RCD (MIN)
CK = 3.75ns, BL = 4, AL = 3, CL = 4,
NOP
T4
83
t FAW (MIN)
READ
Bank c
t RRD
Col
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
Bank d
Row
ACT
T6
512Mb: x4, x8, x16 DDR2 SDRAM
Bank z
t RCD
NOP
Row
T6
READ
Bank d
Col
T7
NOP
T7
t
RRD (MIN) = 7.5ns,
NOP
©2004 Micron Technology, Inc. All rights reserved.
T8
NOP
T8
NOP
T9
Operations
t
FAW. This
t
FAW
RD/WR
Bank y
Bank e
Don’t Care
Col
Don’t Care
Row
T9
T10
ACT
t
RC.