mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 55

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 30:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
(V/ns)
Slew
Rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
t
125
83
4.0 V/ns
DS
Δ
0
–
–
–
–
–
–
DDR2-400/DDR2-533
All units are shown in picoseconds
t
DH
45
21
Δ
0
–
–
–
–
–
–
Notes:
t
125
–11
3.0 V/ns
83
DS
Δ
0
–
–
–
–
–
1. For all input signals, the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be obtained
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 32 on page 57 are the DQS
t
–14
DH
45
21
Δ
0
–
–
–
–
–
value to the derating value listed in Table 30.
t
of V
defined as the slew rate between the last crossing of V
V
the shaded “V
Figure 30 on page 59). If the actual signal is later than the nominal slew rate line anywhere
between the shaded “V
signal from the AC level to DC level is used for the derating value (see Figure 31 on
page 59).
t
ing of V
nal is defined as the slew rate between the last crossing of V
of V
shaded “DC level to V
Figure 32 on page 60). If the actual signal is earlier than the nominal slew rate line any-
where between shaded “DC to V
actual signal from the DC level to V
on page 60).
will not have reached V
signal is still required to complete the transition and reach V
by linear interpolation.
characterization.
single-ended slew rate derating with DQS referenced at V
levels
trip points to DQs referenced to V
page 58. Table 34 on page 58 provides the V
and
for the DQ (
DS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
DH nominal slew rate for a rising signal is defined as the slew rate between the last cross-
IL
(
AC
t
125
REF
–11
–25
REF
t
2.0 V/ns
DS
83
Δ
DH
0
–
–
–
–
) MAX. If the actual signal is always earlier than the nominal slew rate line between
t
DS
(
(DC). If the actual signal is always later than the nominal slew rate line between the
t
DC
IL
a
DS,
) for DDR2-533. Table 35 on page 58 provides the V
(
b
) and the first crossing of V
DC
t
–14
–31
and
DH
45
21
Δ
0
–
–
–
–
t
) MAX and the first crossing of V
DS
t
DH Derating Values with Differential Strobe
REF
t
a
DQS, DQS# Differential Slew Rate
DH
t
–13
–31
and
(
95
12
1.8 V/ns
DS
Δ
1
DC
–
–
–
–
b
. Converting the derated base values from DQs referenced to the AC/DC
) to AC region,” use the nominal slew rate for the derating value (see
t
REF
DH
t
–19
–42
IH
DH
33
12
–2
REF
Δ
–
–
–
–
(
a
DC
[
AC
) for DDR2-400.
(
DC
) region,” use the nominal slew rate for the derating value (see
]/V
55
t
–19
–43
) to AC region,” the slew rate of a tangent line to the actual
t
1.6 V/ns
DS
24
13
–1
Δ
–
–
–
–
DS and
IL
[
REF
AC
REF
REF
] at the time of the rising clock transition), a valid input
t
(
–30
–59
DH
24
10
–7
DC
Δ
IH
–
–
–
–
is listed in Table 34 on page 58 and Table 35 on
(
t
(
DC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
) region,” the slew rate of a tangent line to the
DH required is calculated by adding the data sheet
AC
) level is used for the derating value (see Figure 33
) MIN.
t
–31
–74
25
11
1.4 V/ns
DS
–7
Δ
–
–
–
–
REF
REF
512Mb: x4, x8, x16 DDR2 SDRAM
-based fully derated values for the DQ (
(
t
t
DC
–18
–47
–89
DS nominal slew rate for a falling signal is
DH
22
Δ
5
–
–
–
–
).
t
DH nominal slew rate for a falling sig-
–127 –140 –115 –128 –103 –116
t
REF
–19
–62
1.2 V/ns
DS
23
Input Slew Rate Derating
Δ
5
–
–
–
–
REF
(
DC
IH
REF
and DQ referenced at the logic
) and the first crossing of
IH
t
–35
–77
(
DH
17
–6
DC
Δ
(
–
–
–
–
AC
-based fully derated values
©2004 Micron Technology, Inc. All rights reserved.
) MIN and the first crossing
)/V
t
–50
IL
17
1.0 V/ns
DS
–7
Δ
–
–
–
–
–
(
AC
).
t
–23
–65
DH
Δ
6
–
–
–
–
–
t
–38
0.8 V/ns
DS
Δ
5
–
–
–
–
–
–
t
–11
–53
t
DH
DS
Δ
–
–
–
–
–
–
a