mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 115

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

RESET
CKE LOW Anytime
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM
device resumes normal operation after reinitializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (V
V
operation. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during
RESET with the exception of CKE.
WRITE burst), the memory controller must satisfy the timing parameter
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before
CKE is raised HIGH, at which time the normal initialization sequence must occur (see
"Initialization" on page 70). The DDR2 SDRAM device is now ready for normal operation
after the initialization sequence. Figure 82 on page 116 shows the proper sequence for a
RESET operation.
If CKE asynchronously drops LOW during any valid operation (including a READ or
REF
) are stable and meet all DC specifications prior to, during, and after the RESET
115
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
©2004 Micron Technology, Inc. All rights reserved.
DD
, V
DD
Q, V
t
DELAY before
Operations
DD
L, and