mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 113

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 79:
Figure 80:
Precharge Power-Down Clock Frequency Change
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
PRECHARGE Command-to-Power-Down Entry
LOAD MODE Command-to-Power-Down Entry
Notes:
Notes:
Command
1. The earliest precharge power-down entry may occur is at T2, which is 1 ×
Command
1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and
3. The earliest precharge power-down entry is at T3, which is after
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequen-
cies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. When the input clock frequency is changed,
Address
Address
CHARGE command. Precharge power-down entry occurs prior to
CK#
CKE
CK#
A10
CKE
CK
CK
Valid
T0
Valid
T0
t RP 2
Valid 1
LM
T1
113
Single bank
All banks
Valid
PRE
T1
vs.
1 x
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t MRD
CK
NOP
Power-down 1
T2
512Mb: x4, x8, x16 DDR2 SDRAM
entry
t
NOP
RP met prior to issuing LM command.
T2
Power-down 3
entry
NOP
T3
t
CKE (MIN)
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t
T3
t
MRD is satisfied.
RP (MIN) being satisfied.
t CKE (MIN)
Don’t Care
t
CK after the PRE-
T4
Operations
Don’t Care