mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 117

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

ODT Timing
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Once a 12ns delay (
enabled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate either in synchronous mode or asynchronous mode,
depending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 83 on page 118.
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]),
Figure 85 on page 119.
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
t
ODT turn-off timing, prior to entering any power-down mode, is determined by the
parameter
signal satisfies
(MIN) is satisfied,
shows the example where
occur until state T3. When
apply.
ODT turn-on timing prior to entering any power-down mode is determined by the
parameter
satisfies
satisfied,
where
When
ODT turn-off timing after exiting any power-down mode is determined by the parameter
t
fies
fied,
t
is not satisfied,
ODT turn-on timing after exiting either slow-exit power-down mode or precharge
power-down mode is determined by the parameter
on page 122. At state Ta1, the ODT HIGH signal satisfies
power-down mode at state T1. When
parameters apply. Figure 90 also shows the example where
because ODT HIGH occurs at state Ta0. When
timing parameters apply.
AONPD and
AXPD (MIN), as shown in Figure 89 on page 121. At state Ta1, the ODT LOW signal satis-
AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0. When
t
AXPD (MIN) after exiting power-down mode at state T1. When
t
AOFD and
t
t
ANPD (MIN) is not satisfied,
ANPD (MIN) is not satisfied because ODT HIGH does not occur until state T3.
t
ANPD (MIN) prior to entering power-down mode at T5. When
t
AOND and
t
t
ANPD (MIN), as shown in Figure 87 on page 120. At state T2, the ODT HIGH
ANPD, as shown in Figure 88 on page 120. At state T2, the ODT HIGH signal
t
AOND,
t
AOFPD timing parameters are applied, as shown in Figure 86 on page 119.
t
t
ANPD (MIN) prior to entering power-down mode at T5. When
AOFPD timing parameters apply.
t
AOF timing parameters apply. Figure 89 also shows the example where
t
AOFD and
t
MOD) has been satisfied, and after the ODT function has been
t
AON,
t
AON timing parameters apply. Figure 88 also shows the example
t
ANPD (MIN) is not satisfied because ODT HIGH does not
t
t
ANPD (MIN) is not satisfied,
AOFD, and
117
t
AOF timing parameters apply. Figure 87 on page 120 also
t
AONPD timing parameters apply.
t
AXPD (MIN) is satisfied,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
AOF timing parameters are applied, as shown in
512Mb: x4, x8, x16 DDR2 SDRAM
t
AXPD (MIN) is not satisfied,
t
AXPD (MIN), as shown in Figure 90
t
t
AXPD (MIN) after exiting
AOFPD timing parameters
t
AXPD (MIN) is not satisfied
©2004 Micron Technology, Inc. All rights reserved.
t
AOND and
t
AXPD (MIN) is satis-
t
ANPD (MIN) is
Operations
t
AXPD (MIN)
t
AON timing
t
AONPD
t
ANPD