mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 12

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 3:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
M8, M3, M7,
N2, N8, N3,
N7, P2, P8,
Number
x16 Ball
P3, M2,
P7, R2
J8, K8
L2, L3
K2
L8
–
FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions
x4, x8 Ball
H8, H3, H7,
J7, K2, K8,
J2, J8, J3,
Number
K3, H2,
K7, L2,
G2, G3,
E8, F8
G8
L8
F2
–
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A11, A12,
BA0, BA1
A11, A12
A9, A10,
A9, A10,
Symbol
CK, CK#
A13
CKE
CS#
Input
Input
Input
Input
Input
Input
Type
Description
Address inputs: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all
banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Address inputs: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all
banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Bank address inputs: BA0–BA1 define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1 define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data (DQ and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the
DDR2 SDRAM configuration and operating mode. CKE LOW
provides PRECHARGE power-down and SELF REFRESH
operations (all banks idle), or active power-down (row active in
any bank). CKE is synchronous for power-down entry, power-
down exit, OUTPUT DISABLE, and for self refresh entry. CKE is
asynchronous for SELF REFRESH exit. Input buffers (excluding
CK, CK#, CKE, and ODT) are disabled during power-down. Input
buffers (excluding CKE) are disabled during SELF REFRESH. CKE
is an SSTL_18 input but will detect a LVCMOS LOW level once
V
stable during the power-on and initialization sequence, it must
be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation, V
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
rank selection on systems with multiple ranks. CS# is considered
part of the command code.
DD
12
is applied during first power-up. After V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
512Mb: x4, x8, x16 DDR2 SDRAM
REF
©2004 Micron Technology, Inc. All rights reserved.
must be maintained.
REF
has become