mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 51

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Timing Diagrams
READs
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. G 07/08 EN
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
READ burst operations are initiated with a READ command, as shown in Figure 10 on
page 31. The starting column and bank addresses are provided with the READ
command, and auto precharge is either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the
burst. For the READ commands used in the following illustrations, auto precharge is
disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent data-
out element will be valid nominally at the next positive or negative clock edge. Figure 21
on page 52 shows general timing for each possible CAS latency setting. DQS is driven by
the Mobile DDR SDRAM along with output data. The initial LOW state on DQS is known
as the read preamble; the LOW state coincident with the last data-out element is known
as the read postamble. The READ burst is considered complete when the read post-
amble is satisfied.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of
window hold), and the valid data window is depicted in Figure 28 on page 59 and
Figure 29 on page 60. A detailed explanation of
t
Data from any READ burst may be truncated by a READ or WRITE command to the
same or alternate bank, by a BURST TERMINATE command, or by a PRECHARGE
command to the same bank, provided that the auto precharge mode was not activated.
Data from any READ burst may be concatenated with or truncated with data from a
subsequent READ command. In either case, a continuous flow of data can be main-
tained. The first data element from the new burst either follows the last element of a
completed burst or the last desired data element of a longer burst which is being trun-
cated. The new READ command should be issued x cycles after the first READ
command, where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture). This is shown in Figure 22 on page 53.
A READ command can be initiated on any clock cycle following a previous READ
command. Nonconsecutive read data is shown in Figure 23 on page 54. Full-speed
random read accesses within a page (or pages) can be performed as shown in Figure 24
on page 55.
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 25 on page 56. The BURST TERMINATE latency is equal to the READ
(CAS) latency; for example, the BURST TERMINATE command should be issued x cycles
after the READ command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
RRD.
AC (data-out transition skew to CK) is depicted in Figure 30 on page 61.
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ (valid data-out skew),
1Gb: x16, x32 Mobile DDR SDRAM
t
DQSCK (DQS transition skew to CK) and
©2007 Micron Technology, Inc. All rights reserved
Timing Diagrams
t
QH (data-out