mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 46

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

CAS Latency (CL)
Figure 17:
Operating Mode
Extended Mode Register
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. G 07/08 EN
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ
command and the availability of the first output data. The latency can be set to 2 or 3
clocks, as shown in Figure 17 on page 46.
For CL = 3, if the READ command is registered at clock edge n, then the data will be
nominally available at (n + 2 clocks +
at clock edge n, then the data will be nominally available at (n + 1 clock +
The normal operating mode is selected by issuing a LOAD MODE REGISTER command
with bits A[7:n] each set to zero, and bits A[6:0] set to the desired values.
All other combinations of values for A[7:n] are reserved for future use. Reserved states
should not be used because unknown operation or incompatibility with future versions
may result.
The extended mode register controls additional functions beyond those set by the mode
registers. These additional functions include drive strength, TCSR, and PASR.
Command
Command
DQS
DQS
DQ
DQ
CK#
CK#
CK
CK
READ
READ
T0
T0
CL - 1
CL = 2
CL - 1
46
NOP
NOP
T1
T1
t
AC
CL = 3
T1n
t
Transitioning Data
AC). For CL = 2, if the READ command is registered
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
1Gb: x16, x32 Mobile DDR SDRAM
NOP
OUT
T2
NOP
n
T2
t
AC
T2n
D
n + 1
T2n
OUT
D
D
n + 2
T3
OUT
NOP
NOP
n
OUT
T3
Don’t Care
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T3n
D
n + 3
D
n + 1
T3n
OUT
OUT
t
Operations
AC).