mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 23

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef82ce3074/Source: 09005aef82cd0158
1gb_ddr_mobile_sdram_t48m_density__2.fm - Rev. G 07/08 EN
10. Clock frequency change is supported only during a clock stop, power-down, or self-refresh
11.
12. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8]. For
13. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/
14. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and
15. These parameters guarantee device timing but are not tested on each device.
16. The valid data window is derived by achieving other specifications:
17.
18.
19.
20. Fast command/address input slew rate
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for all
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (
9. Timing tests may use a V
tions (generally a coaxial transmission line terminated at the tester electronics). For the
half-strength driver with a nominal 10pF load, parameters
in the same range. However, these parameters are not subject to production test but are
estimated by design/characterization. Use of IBIS or other simulation tools for system design
validation is suggested.
which CK and CK# cross; the input reference voltage level for signals other than CK/CK# is
V
parameters.
clock at which the READ command was registered; for CL = 3, the first data element is valid
at (2 ×
ing is still referenced to V
erence voltage level is V
mode.
t
higher integer.
x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
DM/DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to
and
is uncertain.
addresses) are measured between V
V
t
cycle and a practical data valid window can be derived. The clock is provided a maximum
duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55
ratio.
t
inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the device
output is no longer driving (
t
V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain.
DAL = (
QH (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
DD
IL
I/O
(
AC
Q/2.
t
Full-drive strength
DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality
t
) for falling input signals.
HP -
t
CK +
t
t
WR/
LZ transitions occur in the same access time windows as valid data transitions.
t
50
QHS). The data valid window derates directly proportional with the clock duty
t
t
CK) + (
AC) after the first clock at which the READ command was registered.
t
RP/
20pF
t
DD
IL
CK): for each term, if not already an integer, round to the next
t
DD
CL (MIN) and
-to-V
Q/2.
t
Q/2 or to the crossing point for CK/CK#. The output timing ref-
t
DQSCK (MAX) +
23
HZ) or begins driving (
I/O
IH
swing of up to 1.5V in the test environment, but input tim-
Half-drive strength
IL
(
DC
≥
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CH (MIN) actually applied to the device CK and CK#
1 V/ns. Slow command/address input slew rate
50
) to V
1Gb: x16, x32 Mobile DDR SDRAM
t
RPST (MAX) condition.
IH
(
AC
) for rising input signals and V
10pF
t
LZ).
Electrical Specifications
t
AC and
t
IH has 0ps added, therefore, it
©2007 Micron Technology, Inc. All rights reserved
t
IS has an additional 50ps
t
t
QH are expected to be
HP (
t
CK +
t
CK/2),
t
AC) after the
t
DQSQ, and
IH
(
DC
) to
≥
t
DS
0.5