mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 48

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 18:
Status Read Register (SRR)
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. G 07/08 EN
En + 2
0
0
1
1
En + 1
Extended Mode Register
En
0
1
0
1
0
–
Notes:
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
...
0
–
E10
0
–
E9
1. The SDRAM must be properly initialized and in the idle or all banks precharged state.
2. Issue a LOAD MODE REGISTER command with BA[1:0] = “01.”
3. Wait
4. Issue a READ command with all address pins set to “0.”
5. Subsequent commands to the SDRAM must be issued
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
2. The integer n is equal to the most significant address bit.
The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh
multiplier, width type, and density of the Mobile SDRAM, as shown in Figure 20 on
page 50. The SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and
BA1 = 0. The sequence to perform an SRR command is as follows:
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first
bit of the burst, with the output being “Don’t Care” on the second bit of the burst.
0
–
n+2
1
mand is issued; only NOPs or DESELECTS are supported during
page 49).
BA1
E8
0
–
n+1
0
BA0
t
E7–E0
Valid
SRR; only NOP or DESELECT commands are supported during the
–
An
n
...
Normal AR Operation
All other states reserved
Operation
...
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10
E7
0
0
0
0
1
1
1
1
E6
0
0
1
1
0
0
1
1
9
E5
0
1
0
1
0
1
0
1
8
48
7
DS
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
E2
0
0
0
0
1
1
1
1
1Gb: x16, x32 Mobile DDR SDRAM
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
Partial-Array Self Refresh Coverage
Full array
Half array
Quarter array
Reserved
Reserved
One-eighth array
One-sixteenth array
Reserved
PASR
1
t
SRC after the SRR READ com-
0
©2007 Micron Technology, Inc. All rights reserved
Address bus
Extended mode
register (Ex)
t
SRC (Figure 19 on
Operations
t
SRR time.