s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 98

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator (ICG) Module
8.4.4.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock
(ICLK), whose clock period is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]).
Because of the digital nature of the DCO, the clock period of ICLK will change in quantized steps. This
will create a clock period difference or quantization error (Q-ERR) from one cycle to the next. Over several
cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202 percent to
0.368 percent. The dependence of this error on the DDIV[3:0] value and the number of cycles the error is
measured over is shown in
8.4.4.2 Binary Weighted Divider
The binary weighted divider divides the output of the ring oscillator by a power of two, specified by the
DCO divider control bits (DDIV[3:0]). DDIV maximizes at %1001 (values of %1010 through %1111 are
interpreted as %1001), which corresponds to a divide by 512. When DDIV is %0000, the ring oscillator’s
output is divided by 1. Incrementing DDIV by one will double the period; decrementing DDIV will halve the
period. The DLF cannot directly increment or decrement DDIV; DDIV is only incremented or decremented
when an addition or subtraction to DSTG carries or borrows.
8.4.4.3 Variable-Delay Ring Oscillator
The variable-delay ring oscillator’s period is adjustable from 17 to 31 stage delays, in increments of two,
based on the upper three DCO stage control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17
stage delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45
percent to 11.8 percent effect on the output frequency. This also corresponds to the size correction made
when the frequency error is greater than ±15 percent. The value of the binary weighted divider does not
affect the relative change in output clock period for a given change in DSTG[7:5].
98
%0101–%1001 (max)
%0000 (min)
%0000 (min)
%0000 (min)
DDIV[3:0]
%0001
%0001
%0001
%0010
%0010
%0010
%0011
%0011
%0100
%0100
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Table
Table 8-2. Quantization Error in ICLK
8-2.
ICLK Cycles
≥ 32
≥ 16
≥ 8
≥ 4
≥ 2
≥ 1
1
4
1
4
1
4
1
1
Bus Cycles
NA
≥ 8
NA
≥ 4
NA
≥ 2
NA
≥ 1
NA
≥ 1
≥ 1
1
1
1
0.202%–0.368%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
0.806%–1.47%
0.806%–1.47%
6.45%–11.8%
1.61%–2.94%
3.23%–5.88%
1.61%–2.94%
τ
ICLK
Q-ERR
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