s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 142

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s908ey16g2vfar

Manufacturer Part Number
s908ey16g2vfar
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Enhanced Serial Communications Interface (ESCI) Module
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
Slow Data Tolerance
142
Figure 13-7
error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop
bit data samples at RT8, RT9, and RT10.
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in
when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is:
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in
when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
shows how much a slow received character can be misaligned without causing a noise
RECEIVER
RT CLOCK
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
MSB
154 147
------------------------- -
170 163
------------------------- -
Figure 13-7. Slow Data
154
170
Figure
Figure
×
×
13-7, the receiver counts 154 RT cycles at the point
13-7, the receiver counts 170 RT cycles at the point
100
100
SAMPLES
=
=
DATA
4.54%
4.12%
STOP
Freescale Semiconductor

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