s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 89

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

8.3.2.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock
(ICLK). The clock period of ICLK is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]).
Because of only a limited number of bits in DDIV and DSTG, the precision of the output (ICLK) is restricted
to a precision of approximately ±0.202 percent to ±0.368 percent when measured over several cycles (of
the desired frequency). Additionally, since the propagation delays of the devices used in the DCO ring
oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require
alternately running faster and slower than desired, making the worst case cycle-to-cycle frequency
variation ±6.45 percent to ±11.8 percent (of the desired frequency). The valid values of DDIV:DSTG range
from $000 to $9FF. For more information on the quantization error in the DCO, see
Error in DCO
8.3.2.2 Modulo N Divider
The modulo N divider creates the low-frequency base clock (IBASE) by dividing the internal clock (ICLK)
by the ICG multiplier factor (N), contained in the ICG multiplier register (ICGMR). When N is programmed
to a $01 or $00, the divider is disabled and ICLK is passed through to IBASE undivided. When the internal
clock generator is stable, the frequency of IBASE will be equal to the nominal frequency (f
kHz ± 25 percent.
Freescale Semiconductor
VOLTAGE AND
ICGEN
REFERENCES
CURRENT
Output.
NAME
NAME
Figure 8-3. Internal Clock Generator Block Diagram
CONFIGURATION REGISTER BIT
TOP LEVEL SIGNAL
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
– –
++
–
+
CLOCK GENERATOR
COMPARATOR
FREQUENCY
TRIM[7:0]
DIGITAL
FILTER
LOOP
CONTROLLED
OSCILLATOR
DIGITALLY
MODULO
DIVIDER
N[6:0]
N
NAME
NAME
Functional Description
8.4.4 Quantization
REGISTER BIT
MODULE SIGNAL
NOM
DSTG[7:0]
DDIV[3:0]
FICGS
IBASE
ICLK
) of 307.2
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