s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 245

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

not exit monitor mode in this situation. Once the reset vector has been programmed, the traditional
method of applying a voltage, V
When the forced monitor mode is entered the COP is always disabled regardless of the state of IRQ or
RST.
With V
internal operating frequency is automatically set to the external frequency divided by four.
With V
nominal 2.45 MHz and the baud rate is a nominal 9600.
19.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
Table 19-2
19.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
19.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
Freescale Semiconductor
DD
SS
User
Monitor
Modes
on IRQ at the monitor entry, the ICG is on. In this case, the internal operating frequency is a
on IRQ, an external oscillator of 9.8034 MHz is required for a baud rate of 9600, as the internal
summarizes the differences between user mode and monitor mode.
START
Vector High
BIT
$FEFE
$FFFE
Reset
0
BIT 0
1
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
2
BIT 1
Vector Low
MISSING STOP BIT
3
TST,
Figure 19-12. Monitor Data Format
$FFFF
$FEFF
Reset
Figure 19-13. Break Transaction
4
to IRQ must be used to re-enter monitor mode after the next POR.
BIT 2
Table 19-2. Mode Differences
5
6
BIT 3
Vector High
7
$FEFC
$FFFC
Break
BIT 4
Functions
BIT 5
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
Vector Low
$FEFD
$FFFD
Break
BIT 6
0
1
BIT 7
2
Vector High
3
STOP
BIT
$FEFC
$FFFC
SWI
4
START
NEXT
5
BIT
6
Monitor Module (MON)
Vector Low
7
$FFFD
$FEFD
SWI
245