s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 166

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.3.2 Active Resets from Internal Sources
An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, POR, or
MENRST as shown in
The COP reset is asynchronous to the bus clock.
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset (POR) module generates a pulse to indicate
that power-on has occurred. The MCU is held in reset while the SIM counter counts out 4096 CGMXCLK
cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the
reset vector sequence to occur.
At power-on, these events occur:
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A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the internal clock generator.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
CGMXCLK
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM asserts IRST. The internal reset signal then follows
with the 64-cycle phase as shown in
RST
IAB
Figure
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Reset Type
All Others
POR/LVI
14-4.
ILLEGAL ADDRESS RESET
Figure 14-4. Sources of Internal Reset
ILLEGAL OPCODE RESET
Table 14-2. Reset Recovery Timing
RST PULLED LOW BY MCU
Figure 14-5. Internal Reset Timing
COP RESET
32 CYCLES
MENRST
POR
LVI
NOTE
Actual Number of Cycles
Figure
4163 (4096 + 64 + 3)
67 (64 + 3)
14-5.
INTERNAL RESET
32 CYCLES
VECTOR HIGH
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