s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 185

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

15.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to
the SPDR ($0012). CPHA has no effect on the delay to the start of the transmission, but it does affect the
initial state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the
first SCK cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive
to its active level. The SPI clock rate (selected by SPR1–SPR0) affects the delay from the write to SPDR
and the start of the SPI transmission. (See
free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits
(SPCR) are set to conserve power. SCK edges occur half way through the low time of the internal MCU
clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative
to the slower SCK. This uncertainty causes the variation in the initiation delay shown in
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
15.6 Error Conditions
Two flags signal SPI error conditions:
Freescale Semiconductor
1. Overflow (OVRF in SPSCR) — Failing to read the SPI data register before the next byte enters the
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the voltage on the slave select
CAPTURE STROBE
FOR REFERENCE
shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and
control register.
pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
FROM MASTER
SCK CPOL = 0
SCK CYCLE #
SCK CPOL =1
FROM SLAVE
SS TO SLAVE
MOSI
MISO
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Figure 15-5. Transmission Format (CPHA = 1)
MSB
MSB
1
BIT 6
BIT 6
2
Figure
BIT 5
BIT 5
3
15-6.) The internal SPI clock in the master is a
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
Figure
LSB
8
Error Conditions
LSB
15-6. This
185