s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 240

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Development Support
19.3 Monitor Module (MON)
The monitor module allows debugging and programming of the microcontroller unit (MCU) through a
single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher
test voltage, V
requirements for in-circuit programming.
Features of the monitor module include:
19.3.1 Functional Description
Figure 19-8
The monitor module receives and executes commands from a host computer.
and
computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
Table 19-1
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
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unauthorized users.
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Figure 19-11
Normal user-mode pin functionality
One pin dedicated to serial communication between MCU and host computer
Standard non-return-to-zero (NRZ) communication with host computer
Standard communication baud rate (9600 @ 2.4576-MHz internal operating frequency)
Execution of code in random-access memory (RAM) or FLASH
FLASH memory security feature
FLASH memory programming interface
Use of external 9.8304 MHz oscillator or ICG to generate internal operating frequency of
2.4576 MHz
Monitor mode entry without high voltage, V
$FF)
Normal monitor mode entry if V
If $FFFE and $FFFF are erased or programmed:
–
–
If $FFFE and $FFFF contain $FF (erased state):
–
–
If $FFFE and $FFFF contain $FF (erased state):
–
–
The external clock is 9.8304 MHz (9600 baud)
IRQ = V
The external clock is 9.8304 MHz (9600 baud)
IRQ = V
The ICG clock is nominal 2.45 MHz (nominal 9600 baud)
IRQ = V
shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
shows a simplified diagram of the monitor mode.
TST
, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware
show example circuits used to enter monitor mode and communicate with a host
TST
DD
SS
(this can be implemented through the internal IRQ pullup)
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
TST
(1)
is applied to IRQ
TST
, if reset vector is blank ($FFFE and $FFFF contain
Figure
Freescale Semiconductor
19-9,
Figure
19-10,