s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 108

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s908ey16g2vfar

Manufacturer Part Number
s908ey16g2vfar
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Internal Clock Generator (ICG) Module
DDIV3:DDIV0 — ICG DCO Divider Control Bits
8.7.7 ICG DCO Stage Register
DSTG7:DSTG0 — ICG DCO Stage Control Bits
108
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A through $F are interpreted the same as $9. Since the DCO is active during
reset, reset has no effect on DSTG and the value may vary.
These bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. The
total number of stages is approximately equal to $1FF, so changing DSTG from $00 to $FF will
approximately double the period. Incrementing DSTG will increase the period (decrease the
frequency) by 0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG cannot
be written when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is
controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG
and the value may vary.
Address: $003A
Reset:
Read:
Write:
DSTG7
Figure 8-15. ICG DCO Stage Control Register (ICGDSR)
Bit 7
R
R
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
= Reserved
DSTG6
R
6
DSTG5
R
5
DSTG4
Unaffected by reset
R
4
DSTG3
R
3
DSTG2
R
2
DSTG1
R
1
Freescale Semiconductor
DSTG0
Bit 0
R

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