s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 194

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
15.13 I/O Registers
Three registers control and monitor SPI operation:
15.13.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
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This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 15-4
identical CPOL bits. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 15-4
identical CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1
between bytes. (See
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register from the data register. Therefore,
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR $0010)
SPI status and control register (SPSCR $0011)
SPI data register (SPDR $0012)
Enables SPI module interrupt requests
Selects CPU interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address:
and
and
Reset:
Read:
Write:
Figure
Figure
$000D
SPRIE
Bit 7
Figure
R
0
15-5.) To transmit data between SPI modules, the SPI modules must have
15-5.) To transmit data between SPI modules, the SPI modules must have
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Figure 15-12. SPI Control Register (SPCR)
= Reserved
15-11). Reset sets the CPHA bit.
R
6
0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
SPWOM
2
0
SPE
1
0
Freescale Semiconductor
SPTIE
Bit 0
0