mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 37
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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Terminology and Notational Conventions
Table ii shows notational conventions used throughout this document.
<ea>y,<ea>x
Instruction
PSTDDATA
MACSR
#<data>
<label>
<shift>
<size>
MASK
Dy,Dx
Ry,Rx
Ay,Ax
<list>
CCR
Í
ACC
Rm
Rw
PC
SR
An
Dn
Rc
Rn
bc
dc
cc
Xi
Effective address
Logical condition (example: NE for not equal)
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Any data register n (example: D5 is data register 5)
Source and destination data registers, respectively
Any control register (example VBR is the vector base register)
MAC registers (ACC, MAC, MASK)
Any address or data register
Destination register w (used for MAC instructions only)
Any source and destination registers, respectively
index register i (can be an address or data register: Ai, Di)
MAC accumulator register
Condition code register (lower byte of SR)
MAC status register
MAC mask register
Program counter
Status register
Processor status/debug data port
Immediate data following the 16-bit operation word of the instruction
Source and destination effective addresses, respectively
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
Shift operation: shift left (<<), shift right (>>)
Operand data size: byte (B), word (W), longword (L)
Both instruction and data caches
Data cache
Freescale Semiconductor, Inc.
For More Information On This Product,
Table ii Notational Conventions
Go to: www.freescale.com
Miscellaneous Operands
Register Specifications
About This Book
Opcode Wildcard
Register Names
Port Name
Operand Syntax
Terminology and Notational Conventions
xxxvii
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