mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 24
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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Figure
Number
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
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18-34
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20-19
xxiv
Longword Read from an 8-Bit Port, External Termination...................................... 18-16
Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16
Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17
Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17
Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20
Basic No-Wait-State External Master Access .......................................................... 18-22
External Master Burst Line Access to 32-Bit Port.................................................... 18-24
MCF5307 Two-Wire Mode Bus Arbitration Interface............................................. 18-25
Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26
Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27
MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28
Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30
Three-Wire Bus Arbitration...................................................................................... 18-31
Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32
Master Reset Timing................................................................................................. 18-34
Software Watchdog Reset Timing ............................................................................ 18-36
JTAG Test Logic Block Diagram ............................................................................... 19-2
JTAG TAP Controller State Machine......................................................................... 19-4
Disabling JTAG in JTAG Mode ............................................................................... 19-11
Disabling JTAG in Debug Mode .............................................................................. 19-11
Clock Timing .............................................................................................................. 20-3
PSTCLK Timing......................................................................................................... 20-3
AC Timings—Normal Read and Write Bus Cycles ................................................... 20-5
SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO.............................. 20-6
SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO............................. 20-7
SDRAM Read Cycle with EDGESEL Tied High....................................................... 20-8
SDRAM Write Cycle with EDGESEL Tied High...................................................... 20-9
SDRAM Read Cycle with EDGESEL Tied Low ..................................................... 20-10
SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-11
AC Output Timing—High Impedance...................................................................... 20-11
Reset Timing............................................................................................................. 20-12
Real-Time Trace AC Timing .................................................................................... 20-13
BDM Serial Port AC Timing .................................................................................... 20-13
Timer Module AC Timing ........................................................................................ 20-14
I
UART0/1 Module AC Timing—UART Mode......................................................... 20-17
General-Purpose I/O Timing..................................................................................... 20-18
DMA Timing ............................................................................................................ 20-19
IEEE 1149.1 (JTAG) AC Timing ............................................................................. 20-21
2
C Input/Output Timings......................................................................................... 20-16
Freescale Semiconductor, Inc.
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MCF5307 User’s Manual
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