mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 118
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
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Set 0
Set 127
Cache Operation
4-20
After reset, the cache is
invalidated, ways 0 and 1
are then written with data
that should not be
deallocated.
A:Ways 0 and 1 are filled.
Way 0 Way 1 Way 2 Way 3
Ways 2 and 3 are
invalid.
Invalid (V = 0)
Valid, not modified (V = 1, M = 0)
Valid, modified (V = 1, M = 1)
Freescale Semiconductor, Inc.
For More Information On This Product,
B:CACR[DHLCK] is set,
After CACR[HLCK] is
set, subsequent cache
accesses go to ways 2
and 3.
Way 0 Way 1 Way 2 Way 3
locking ways 0 and 1.
Figure 4-7. Cache Locking
Go to: www.freescale.com
MCF5307 User’s Manual
C:When a set in Way 2 is
While the cache is
locked and after a
position in ways is full,
the set in Way 3 is
updated.
Way 0 Way 1 Way 2 Way 3
occupied, the set in way 3
is used for a cacheable
access.
D:Write hits to ways 0
While the cache is
locked, ways 0 and 1 can
be updated by write hits.
In this example, memory
is configured as
copyback, so updated
cache lines are marked
modified.
Way 0 Way 1 Way 2 Way 3
and 1 update cache
lines.
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