mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 262
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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Synchronous Operation
latency (SCAS assertion to data out), this value is also 2 BCLKO cycles. Notice that
are executed until the last data is read. A
data transfer.
Figure 11-19 shows the burst write operation. In this example, DACR[CASL] = 01, which
creates an SRAS-to-SCAS delay (t
upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read
cycle with the same t
SDRAM cycle until the precharge-to-
11-28
RAS[0] or [1]
CAS[3:0]
DRAMW
BCLKO
D[31:0]
A[31:0]
SRAS
SCAS
ACTV
t
RCD
Row
Figure 11-18. Burst Read SDRAM Access
RCD.
= 2
Freescale Semiconductor, Inc.
NOP
For More Information On This Product,
The next bus cycle is initiated sooner, but cannot begin an
Column Column Column
Go to: www.freescale.com
MCF5307 User’s Manual
RCD
ACTV
t
CASL
) of 2 BCLKO cycles. Note that data is available
PALL
READ
= 2
delay completes.
command is executed one cycle after the last
Column
NOP
NOP
t
EP
PALL
NOP
s
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