mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 288
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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DMA Controller Module Programming Model
12.4.5 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
Figure 12-9. Only a write to DSRn[DONE] results in action.
Table 12-4 describes DSRn fields.
16
15
14–0
12-10
7
6
5
4
3
Bits
Bits
—
CE
BES
BED
—
START
AT
—
Name
Name
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size,
or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by
writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error either during the read portion of a transfer or
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Start transfer.
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the control registers. START is
AT is available only if BCR24BIT = 1.
DMA acknowledge type. Controls whether acknowledge information is provided for the entire
transfer or only the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the
1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information
Reserved, should be cleared.
Address
cleared automatically after one clock and is always read as logic 0.
result of an external request.
is displayed for both the read and write cycles.
during an access in single-address mode (SAA = 1).
Reset
Field
R/W
Table 12-3. DCRn Field Descriptions (Continued)
Figure 12-9. DMA Status Registers (DSRn)
Freescale Semiconductor, Inc.
—
—
7
Table 12-4. DSRn Field Descriptions
For More Information On This Product,
CE
0
6
Go to: www.freescale.com
MBAR + 0x310, 0x350, 0x390, 0x3D0
MCF5307 User’s Manual
BES
0
5
BED
0
4
Description
Description
R/W
—
—
3
REQ
0
2
BSY
0
1
DONE
0
0
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