ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 77
ds26524
Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS26524.pdf
(273 pages)
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Figure 8-13. E1 Transmit Pulse Templates
8.11.2.2
The individual transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control register
(LMCR). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIP
and TRING pins.
When tansmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference. Data
input from the framer is ignored. AIS can be sent by setting a bit in the LMCR. Transmit all ones will also be sent if
the corresponding receiver goes into LOS state and the ATAIS bit is set in the LMCR.
8.11.2.3
Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is
approximately 25Ω or less. SCS (LRSR.2) provides a real-time indication of when the current limiter is activated.
The LIU Latched Status register (LLSR) provides latched versions of the information, which can be used to activate
an interrupt when enabled via the
8.11.2.4
The DS26524 can also detect when the TTIP or TRING outputs are open circuited. OCS (LRSR.1) provides a real-
time indication of when an open circuit is detected. Register
which can be used to activate an interrupt when enabled via the
not available in T1 CSU operating modes (LBO5, LBO6, and LBO7).
Transmit Power-Down
Transmit Short-Circuit Detector/Limiter
Transmit Open-Circuit Detector
-0.1
-0.2
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-250
LSIMR
-200
-150
register.
-100
77 of 273
-50
TIME (ns)
194ns
219ns
0
LLSR
LSIMR
50
provides latched versions of the information,
100
register. The open-circuit detect feature is
150
269ns
Template
G.703
200
250
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