ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 209

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only).
Bit 3: Transmit FIFO Underrun Event (TUDR).
Bit 2: Transmit Message End Event (TMEND).
Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS).
Bit 0: Transmit FIFO Not Full Set Condition (TNFS).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Loss of Frame Synchronization Detect (LOFD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
—
—
7
0
7
0
TIM2
Transmit Interrupt Mask Register 2 (HDLC)
1A1h + (200h x n): where n = 0 to 3, for Ports 1 to 4
TIM3
Transmit Interrupt Mask Register 3 (Synchronizer)
1A2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
—
—
6
0
6
0
—
—
—
5
0
5
0
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TFDLE
—
—
0
0
4
4
TUDR
TUDR
—
3
0
3
0
TMEND
TMEND
—
2
0
2
0
TLWMS
TLWMS
—
1
0
1
0
LOFD
TNFS
TNFS
0
0
0
0