ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 41

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode
8.8.4
The Receive Channel Blocking registers (RCBR1:RCBR4) and the Transmit Channel Blocking registers
(TCBR1:TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-
programmable outputs that can be forced either high or low during individual channels. These outputs can be used
to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to 1,
the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. When used with a T1
(1.544MHz) backplane, only
backplane when the elastic store is configured for T1-to-E1 rate conversion. See Section 8.8.1.
8.8.5 Transmit Fractional Support (Gapped Clock Mode)
The DS26524 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled
via the Transmit Gapped-Clock Channel Select registers (TGCCS1:TGCCS4). The transmit path is enabled for
gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
8.8.6 Receive Fractional Support (Gapped Clock Mode)
The DS26524 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled
via the Receive Gapped-Clock Channel Select registers (RGCCS1:RGCCS4). The receive path is enabled for
gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
TSSYNCIO
TSSYNCIO
TSYSCLK
TSER
Receive and Transmit Channel Blocking Registers
1
2
NOTE 1: TSSYNCIO IN NORMAL OPERATION.
NOTE 2: TSSYNCIO WITH H100EN = 1 and TSSYNCINV = 1.
NOTE 3: t
BIT 8
BC
TCBR1:TCBR2:TCBR3
(BIT CELL TIME) = 122ns (typ). t
t
41 of 273
BC
BIT 1
are used.
3
BC
= 244ns OR 488ns ALSO ACCEPTABLE.
TCBR4
is included to support an E1 (2.048MHz)
BIT 2