ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 179

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Gapped Clock Channel Select Bits for Channels 1 to 32 (CH[1:32]).
*Note that RGCCS4 has two functions:
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channel Idle Code Insertion Control Bits for Channels 1 to 32 (CH[1:32]).
0 = no clock is present on RCHCLK during this channel time
1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the
elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled.
When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on
RCHCLK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is
generated on RCHCLK during the F-bit time:
In this mode, RGCCS4.1:RGCCS4.7 should be set to 0.
0 = do not insert data from the Idle Code Array into the receive data stream
1 = insert data from the Idle Code Array into the receive data stream
(MSB) 7
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
7
0
0
RGCCS4.0 = 0, do not generate a clock during the F-bit.
RGCCS4.0 = 1, generate a clock during the F-bit.
CH15
CH23
CH31
CH7
CH15
CH23
CH31
CH7
RGCCS1, RGCCS2, RGCCS3, RGCCS4
Receive Gapped-Clock Channel Select Registers 1 to 4
0CCh, 0CDh, 0CEh, 0CFh + (200h x n): where n = 0 to 3, for Ports 1 to 4
RCICE1, RCICE2, RCICE3, RCICE4
Receive Channel Idle Code Enable Registers 1 to 4
0D0h, 0D1h, 0D2h, 0D3h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
0
6
0
CH14
CH22
CH30
CH6
CH14
CH22
CH30
CH6
5
0
5
0
CH13
CH21
CH29
CH5
CH13
CH21
CH29
CH5
4
0
4
0
179 of 273
CH12
CH20
CH28
CH4
CH12
CH20
CH28
CH4
3
0
3
0
CH11
CH19
CH27
CH3
CH11
CH19
CH27
2
0
CH3
2
0
CH10
CH18
CH26
CH2
CH10
CH18
CH26
1
0
CH2
1
0
(F-bit)
CH17
CH25
CH1
CH9
0 (LSB)
0
0
CH17
CH25
CH1
CH9
0
RGCCS1
RGCCS2
RGCCS3
RGCCS4*
(E1 Mode
Only)
RCICE1
RCICE2
RCICE3
RCICE4
(E1 Mode
Only)