ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 151
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ds26524
Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS26524.pdf
(273 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 6 and 5: IBO Bus Size Bits (IBS[1:0]). Indicates how many devices on the bus.
Bit 4: Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode.
Bit 3: Interleave Bus Operation Enable (IBOEN).
Bits 2 to 0: Device Assignment Bits (DA[2:0]).
IBS1
DA2
0
0
1
1
0
0
0
0
1
1
1
1
0 = Channel Interleave
1 = Frame Interleave
0 = interleave bus operation disabled
1 = interleave bus operation enabled
IBS0
DA1
0
0
1
1
0
0
1
1
0
1
0
1
—
7
0
DA0
8 devices on bus (16.384MHz)
2 devices on bus (4.096MHz)
4 devices on bus (8.192MHz)
0
1
0
1
0
1
0
1
Reserved for future use
RIBOC
Receive Interleave Bus Operation Control Register
088h + (200h x n): where n = 0 to 3, for Ports 1 to 4
IBS1
6
0
DEVICE POSITION
BUS SIZE
2nd device on bus
3rd device on bus
1st device on bus
4th device on bus
5th device on bus
6th device on bus
7th device on bus
8th device on bus
IBS0
5
0
IBOSEL
151 of 273
0
4
IBOEN
3
0
DA2
2
0
DA1
1
0
DA0
0
0
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