ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 111

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock
source will be used for BPCLK generation. The BPCLK can be generated from the LIU recovered clock, an external
reference, or derivatives of MCLK input. This is shown in
Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the
reference clock frequency used by the DS26524 backplane clock generation circuit. Note that the setting of this bit
should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock.
See
Bit 2: Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, this bit selects the external MCLK
frequency of the signal input at the MCLK pin of the DS26524.
Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select
the external MCLK frequency of the signal input at the MCLK pin of the DS26524. This is shown in
Table 9-11. Backplane Reference Clock Select
BPREFSEL3
Figure 8-1
0
0
0
0
0
0
0
0
1
1
1
1
0 = Backplane reference clock is 2.048MHz.
1 = Backplane reference clock is 1.544MHz.
0 = The external master clock is 2.048MHz or multiple thereof.
1 = The external master clock is 1.544MHz or multiple thereof.
BPREFSEL3
BPREFSEL2
for additional information.
7
0
0
0
0
0
0
0
0
0
0
0
0
0
GTCCR
Global Transceiver Clock Control Register
0F3h
BPREFSEL2
BPREFSEL1
6
0
0
0
0
0
1
1
1
1
0
0
1
1
BPREFSEL1
BPREFSEL0
0
0
1
1
0
0
1
1
0
1
0
0
5
0
111 of 273
BFREQSEL
BPREFSEL0
Table
1
0
0
1
0
1
0
1
0
1
0
1
4
0
9-11. See
2.048MHz RCLK1
1.544MHz RCLK1
2.048MHz RCLK2
1.544MHz RCLK2
2.048MHz RCLK3
1.544MHz RCLK3
2.048MHz RCLK4
1.544MHz RCLK4
1.544MHz derived from MCLK.
(REFCLKIO is an output.)
2.048MHz derived from MCLK.
(REFCLKIO is an output.)
2.048MHz external clock input at REFCLKIO.
(REFCLKIO is an input.)
1.544MHz external clock input at REFCLKIO.
(REFCLKIO is an input.)
BFREQSEL
3
0
Figure 8-1
REFERENCE CLOCK
FREQSEL
for additional information.
SOURCE
2
0
MPS1
1
0
Table
9-12.
MPS0
0
0