ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 69

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

DS26524 Quad T1/E1/J1 Transceiver
8.10.2 Transmit HDLC Controller
8.10.2.1
FIFO Information
The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
8.10.2.2
HDLC Transmit Example
The HDLC status registers in the DS26524 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used. An example routine for using the
DS26524 HDLC receiver is given in
Figure
8-10.
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