ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 199

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: TCLK Invert (TCLKINV).
Bit 6: TSYNC Invert (TSYNCINV).
Bit 5: TSSYNCIO Invert (TSSYNCINV) (Input Mode Only).
Bit 4: TSYSCLK Mode Select (TSCLKM).
Bit 3: TSSYNCIO Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNCIO pin.
Bit 2: TSYNC I/O Select (TSIO).
Bit 1: TSYNC Double-Wide (TSDW) (T1 Mode Only). (Note: This bit must be set to zero when TSM = 1 or when
TSIO = 0.)
Bit 0: TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin.
0 = No inversion
1 = Invert
0 = No inversion
1 = Invert
0 = No inversion
1 = Invert
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048/4.096/8.192MHz or IBO enabled (see Section
0 = frame mode
1 = multiframe mode
0 = TSYNC is an input
1 = TSYNC is an output
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
0 = frame mode
1 = multiframe mode
TCLKINV
TCLKINV
7
0
TSYNCINV
TSYNCINV
TIOCR
Transmit I/O Configuration Register
184h + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
0
TSSYNCINV
TSSYNCINV
5
0
TSCLKM
TSCLKM
199 of 273
4
0
TSSM
TSSM
0
3
8.8.2
TSIO
TSIO
2
0
for details on IBO function)
TSDW
—
1
0
TSM
TSM
0
0