ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 48

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

8.9.4
The DS26524 supports both software- and hardware-based signaling. Interrupts can be generated on changes of
signaling data. The DS26524 is also equipped with receive-signaling freeze on loss of synchronization (OOF),
carrier loss, or change of frame alignment. The DS26524 also has hardware pins to indicate signaling freeze.
Table 8-16. Registers Related to Signaling
Transmit-Signaling Registers 1 to 16
(TS1
Software-Signaling Insertion Enable
Registers 1 to 4
Transmit Hardware-Signaling Channel
Select Registers 1 to 4
(THSCS1
Receive-Signaling Control Register
(RSIGC)
Receive-Signaling All-Ones Insertion
Registers 1 to 3
(T1RSAOI1
Receive-Signaling Registers 1 to 16
(RS1
Receive-Signaling Status Registers 1
to 4
Receive-Signaling Change of State
Enable Registers 1 to 4
RSCSE4)
Receive Latched Status Register 4
(RLS4)
Receive Interrupt Mask Register 4
(RIM4)
Receive-Signaling Reinsertion Enable
Registers 1 to 4
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
•
•
(RSS1
to TS16)
to RS16)
Signaling
Flexible signaling support
o Software or hardware based
o Interrupt generated on change of signaling data
o Receive-signaling freeze on loss of frame, loss of signal, or change of frame alignment
Hardware pins for carrier loss and signaling freeze indication
to THSCS4)
to RSS4)
to T1RSAOI3)
REGISTER
(SSIE1
(RSI1
to RSI4)
(RSCSE1
to SSIE4)
to
1C8h, 1C9h, 1CAh, 1CBh
0C8h, 0C9h, 0CAh, 0CBh
0A8h, 0A9h, 0AAh, 0ABh
FRAMER ADDRESSES
118h, 119h, 11Ah, 11Bh
140h to 14Fh (E1 CAS)
140h to 14Bh (T1/J1)
040h to 04Bh (T1/J1)
098h to 09Ah (T1/J1)
040h to 04Fh (E1)
038h, 039h, 03Ah
98h to 9Fh (E1)
0A3h
013h
093h
48 of 273
Transmit ABCD signaling.
When enabled, signaling is inserted for
the channel.
Bits determine which channels will have
signaling inserted in hardware-signaling
mode.
Freeze control for receive signaling.
Registers for all-ones insertion (T1 mode
only).
Receive-signaling bytes.
Receive-signaling change of status bits.
Receive-signaling change of state
interrupt enable.
Receive-signaling change of state bit.
Receive-signaling change of state
interrupt mask bit.
Registers for signaling reinsertion.
FUNCTION