MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 8

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

Read Latency
tween the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in CAS Latency
Diagram.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
operation or incompatibility with future versions may
result.
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
COMMAND
COMMAND
The READ latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC and nominal t DSDQ
T0
T0
CAS Latency
Diagram
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
184-PIN REGISTERED DDR SDRAM DIMM
T3n
T3n
8
* An additional clock cycle will be incurred when module is in
Operating Mode
MODE REGISTER SET command with bits A7-A12 each
set to zero, and bits A0-A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A9-A12 each set to zero, bit A8
set to one, and bits A0-A6 set to the desired values.
Although not required by the Micron device, JEDEC
specifications recommend when a LOAD MODE REG-
ISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER com-
mand to select normal operating mode.
served for future use and/or test modes. Test modes
and reserved states should not be used because un-
known operation or incompatibility with future ver-
sions may result.
register mode.
The normal operating mode is selected by issuing a
All other combinations of values for A7-A12 are re-
SPEED
-26A
-335
-265
-202
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAS LATENCY (CL)
CLOCK FREQUENCY (MHz)
ALLOWABLE OPERATING
75
75
75
75
TABLE
CL = 2*
f
f
f
f
133
133
100
100
512MB (x72)
PRELIMINARY
75
©2002, Micron Technology, Inc.
75
75
75
CL = 2.5*
f
f
f
f
133
133
125
167