MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 15

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

NOTES
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
10. I
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaran-
teed for the full voltage range specified.
of up to 1.5V in the test environment, but input
timing is still referenced to V
point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew
rate for the input signals used to test the device is
1V/ns in the range between V
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in
that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
DC value. Thus, from V
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
rates. Specified values are obtained with
minimum cycle time at CL = 2 for -26A and -202,
CL = 2.5 for -335 and -265 with the outputs open.
properly initialized, and is averaged at the
defined cycle rate.
DD
DD
REF
TT
is not applied directly to the device. V
is dependent on output loading and cycle
specifications are tested after the device is
is expected to equal V
REF
Output
(V
REF
OUT
by-pass capacitor.
may not exceed ±2 percent of the
DD
)
tests may use a V
V
DD
TT
DD
, and electrical AC and DC
50
30pF
Reference
Point
Q/2, V
DD
SS
REF
Q/2 of the transmit-
REF
.
IL
REF
(
AC
REF
(or to the crossing
and must track
.
) and V
is allowed
IL
-to-V
TT
IH
IH
(
is a
AC
184-PIN REGISTERED DDR SDRAM DIMM
swing
).
15
11. This parameter is sampled. V
12. Command/Address input slew rate = 0.5V/ns. For
13. The CK/CK# input reference level (for timing
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured
16.
17. The maximum limit for this parameter is not a
18. This is not a device limit. The device will operate
19. It is recommended that DQS be valid (HIGH or
20. MIN (
V
25°C, V
0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in
loading.
-265 with slew rates 1V/ns and faster,
are reduced to 900ps. If the slew rate is less than
0.5V/ns, timing must be derated:
additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns.
that is, it remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.
referenced to CK/CK#) is the point at which CK
and CK# cross; the input reference level for
signals other than CK/CK# is V
stabilizes. Exception: during the period before
V
LOW.
at the timing reference point indicated in Note 3,
is V
t
time windows as valid data transitions. These
parameters are not referenced to a specific
voltage level, but specify when the device output
is no longer driving (HZ) or begins driving (LZ).
device limit. The device will operate with a
greater value for this parameter, but system
performance (bus turnaround) will degrade
accordingly.
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
smallest multiple of
absolute value for the respective parameter.
(MAX) for I
multiple of
absolute value for
HZ and
DD
REF
TT
Q = +2.5V ±0.2V, V
stabilizes, CKE
.
t
RC or
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
LZ transitions occur in the same access
(
DC
DD
t
CK that meets the maximum
t
RFC) for I
) = V
measurements is the largest
t
DQSS.
DD
t
RAS.
Q/2, V
t
REF
CK that meets the minimum
0.3 x V
DD
= V
measurements is the
OUT
SS
DD
512MB (x72)
DD
, f = 100 MHz, T
(peak to peak) =
Q is recognized as
REF
t
IH has 0ps added,
PRELIMINARY
= +2.5V ±0.2V,
.
t
IS has an
©2002, Micron Technology, Inc.
t
IS and
REF
A
t
=
t
RAS
IH