MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet

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MT18VDDF6472G-202

Manufacturer Part Number
MT18VDDF6472G-202
Description
184-PIN REGISTERED DDR SDRAM DIMM
Manufacturer
Micron
Datasheet
DDR SDRAM
DIMM
FEATURES
• 184-pin, dual in-line memory modules (DIMM)
• ECC, 1-bit error detection and correction
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce
• Utilizes 333MT/s, 266MT/s, and 200MT/s DDR
• Fast data transfer rates; PC2700, PC2100, or
• 512MB (64 Meg x 72)
• V
• V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• Internal, pipelined double data rate (DDR)
• Bidirectional data strobe (DQS) transmitted/
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent opera-
• Selectable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency
• Gold-plated edge contacts
PART NUMBERS AND TIMING PARAMETERS
NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
DDF18C64x72G_A.p65 – Pub.02/02
64 Meg x72 184 Pin DDR Registered SDRAM DIMM
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
PART NUMBER
MT18VDDF6472G-335__
MT18VDDF6472G-26A__
MT18VDDF6472G-265__
MT18VDDF6472G-202__
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
loading
FBGA SDRAM components
PC1600
aligned with data for WRITEs
architecture; two data accesses per clock cycle
received with data, i.e., source-synchronous data
capture
tion
interval
DD
DDSPD
= V
current revision codes. Example: MT18VDDF6472G-265A1
DD
= +2.3V to +3.6V
Q= +2.5V ±0.2V
MARKING
PART
-26A
-335
-265
-202
MODULE CONFIGURATION
DENSITY
512MB
512MB
512MB
512MB
184-PIN REGISTERED DDR SDRAM DIMMs
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
1
MT18VDDF6472
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/moduleds
ADDRESS TABLE
OPTIONS
• Package
• Memory Clock/Speed, CAS Latency*
*An additional clock cycle will be incurred when module is in registered
Refresh Count
Base Device Configuration
Device Bank Addressing
Device Row Addressing
Device Column Addressing
Module Bank Addressing
mode
184-pin DIMM (gold)
6ns (166 MHz), 333MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
10ns (133 MHz), 200 MT/s, CL = 2
BANDWIDTH
MODULE
2.7 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MEMORY CLOCK/
184-Pin DIMM
DATA BIT RATE
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
6ns/333 MT/s
MO-206
2K (A0–A9, A11)
512MB (x72)
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 4
1 (S0#)
PRELIMINARY
512MB
(CL -
8K
©2002, Micron Technology, Inc.
LATENCY
MARKING
t
2.5-3-3
2.5-3-3
RCD -
2-3-3
2-2-2
-335
-26A
-265
-202
G
t
RP)*

Related parts for MT18VDDF6472G-202

MT18VDDF6472G-202 Summary of contents

Page 1

... MT18VDDF6472G-26A__ -26A MT18VDDF6472G-265__ -265 MT18VDDF6472G-202__ -202 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDF6472G-265A1 64 Meg x72 184 Pin DDR Registered SDRAM DIMM DDF18C64x72G_A.p65 – Pub.02/02 ‡ ...

Page 2

... A12 138 CK0# 161 DQ46 U8 U9 U10 PIN 92 PIN 53 U19 U20 U21 PIN 93 Indicates a V pin SS Micron Technology, Inc., reserves the right to change products or specifications without notice. PIN SYMBOL 162 DQ47 163 NC 164 V DD 165 DQ52 166 DQ53 167 N C 168 ...

Page 3

... BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. V Input SSTL_2 reference voltage. REF 3 PRELIMINARY 512MB (x72) DESCRIPTION is applied. DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 4

... No Connect: These pins should be left unconnected. DNU — Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. 4 PRELIMINARY 512MB (x72) DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 5

... CK# NOTE: 1. All resistor values are 22 ohms unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide optimize system and loading and signal integrity for -335 speed grade modules, 3 (single bank modules (dual bank modules) stub resistors may be placed on command/address and control lines ...

Page 6

... Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or inter- leaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. PRELIMINARY 512MB (x72) ©2002, Micron Technology, Inc. ...

Page 7

... For a burst length of eight, A3-A12 select the eight-data-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Micron Technology, Inc., reserves the right to change products or specifications without notice. PRELIMINARY 0-1 1-0 0-1-2-3 1-0-3-2 ...

Page 8

... CAS LATENCY (CL) TABLE ALLOWABLE OPERATING CLOCK FREQUENCY (MHz -335 75 133 f -26A 75 133 f -265 75 100 f -202 75 100 Micron Technology, Inc., reserves the right to change products or specifications without notice 2. 167 f 75 133 f 75 133 f 75 125 ©2002, Micron Technology, Inc. ...

Page 9

... NOTE: 1. E14 and E13 (BA1 and BA0) must be “0, 1” to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. Extended Mode Register Definition 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. PRELIMINARY 512MB (x72 ...

Page 10

... Micron’s 256Mb DDR SDRAM data sheet. CS# RAS# CAS# WE Micron Technology, Inc., reserves the right to change products or specifications without notice. PRELIMINARY 512MB (x72) ADDR NOTES Bank/Row Bank/Col 4 L ...

Page 11

... OH I 16.8 – OL MIN MAX V + 0.310 – REF – 0.310 REF 0. 0. Micron Technology, Inc., reserves the right to change products or specifications without notice. UNITS NOTES V 32 32, 36 µA 48 µA µA µA 48 ...

Page 12

... TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 7 DD Micron Technology, Inc., reserves the right to change products or specifications without notice. UNITS NOTES 21, 28 21 20, 45 ...

Page 13

... Input Capacitance: Command and Address; S0#; CKE0 Input Capacitance: CK0, CK0# 64 Meg x72 184 Pin Registered DDR SDRAM DIMM DDF18C64x72G_A.p65 – Pub. 02/02 184-PIN REGISTERED DDR SDRAM DIMM 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. PRELIMINARY 512MB (x72) SYMBOL MIN MAX UNITS C 4 ...

Page 14

... QH - DQSQ QH - DQSQ ns 70.3 70.3 µs 7.8 7.8 µ 200 200 CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc 40, 47 40, 47 23 16, 37 16 ...

Page 15

... CK that meets the minimum absolute value for the respective parameter. (MAX) for I measurements is the largest DD t multiple of CK that meets the maximum t absolute value for RAS. Micron Technology, Inc., reserves the right to change products or specifications without notice. = +2.5V ±0.2V and has an . ...

Page 16

... If slew rate exceeds 4V/ns, functionality is uncertain. 3.450 3.400 3.350 3.300 3.100 3.050 3.000 2.950 2.275 2.238 2.200 2.163 47/53 46.5/54.5 46/54 45.5/55.5 Micron Technology, Inc., reserves the right to change products or specifications without notice and DH for 3.250 2.900 2.125 45/55 ©2002, Micron Technology, Inc. ...

Page 17

... HZ(MAX) will prevail over t t RPST(MAX) condition. LZ(MIN) will prevail over t t DQSCK(MIN) + RPRE(MAX) condition. Figure B Pull-Up Characteristics 0 -20 -40 -60 -80 0.0 0.5 1.0 1 (V) DD OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. PRELIMINARY Q+1.5V for a DD 3ns t DQSCK(MAX) + 2.0 2.5 ©2002, Micron Technology, Inc. ...

Page 18

... This is followed by 200 clock cycles. 48. Leakage number reflects the worst case leakage 18 PRELIMINARY 512MB (x72) t REF later. possible through the module pin, not what each memory device contributes. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 19

... NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module Applications Team if further information on the specific register model is required. ...

Page 20

... NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module Applications Team if further information on the specific register model is required. ...

Page 21

... SCL DATA STABLE SDA Figure 3 21 PRELIMINARY 512MB (x72) Figure 2 Definition of Start and Stop START BIT 8 9 Acknowledge Micron Technology, Inc., reserves the right to change products or specifications without notice. STOP BIT ©2002, Micron Technology, Inc. ...

Page 22

... CHIP ENABLE SU:DAT t SU:STO MIN 4 4.7 250 4.7 4.7 Micron Technology, Inc., reserves the right to change products or specifications without notice BUF UNDEFINED MAX UNITS µs µs 1 µs ns µs µs ©2002, Micron Technology, Inc. ...

Page 23

... NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module Applications Team if further information on the specific register model is required. ...

Page 24

... REGISTERED DDR SDRAM DIMM AC) Fast / Conconcurrent A/P t RP) t RRD) t RCD) t RAS) (Note 3) 24 PRELIMINARY 512MB (x72) ENTRY (VERSION) MT18VDDF6472G (Hex) 128 256 SDRAM DDR SSTL 2.5V 6ns (-335) 7ns (-26A) 7.5ns (-265) 8ns (-202) 0.7ns (-335) 0.75ns (-26A/-265) 0.8ns (-202) ECC 7.81µ ...

Page 25

... DS) t DH) t RC) t RFC) 25 PRELIMINARY 512MB (x72) ENTRY (VERSION) MT18VDDF6472G (Hex) 512MB .80ns (-335) 1.0ns (-26A/-265) 1.1ns (-202) .80ns (-335) 1.0ns (-26A/-265) 1.1ns (-202) 0.45ns (-335) 0.5ns (-26A/-265) 0.6ns (-202) 0.45ns (-335) 0.5ns (-26A/-265) 0.6ns (-202) ...

Page 26

... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logos are trademarks of Micron Technology, Inc. 64 Meg x72 184 Pin Registered DDR SDRAM DIMM DDF18C64x72G_A.p65 – Pub. 02/02 ...

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