MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 16

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

NOTES (continued)
21. The refresh period 64ms. This equates to an
22. The valid data window is derived by achieving
23. Referenced to each output group: x4 = DQS with
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
average refresh rate of 7.821µs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3µs; burst refreshing or
posting by the DRAM controller greater than
eight refresh cycles is not allowed.
other specifications -
t
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncer-
tain when operating beyond a 45/55 ratio. The
data valid window derating curves are provided
below for duty cycles ranging between 50/50 and
45/55.
DQ0-DQ3.
QH (
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
QH =
50/50
3.750
2.500
t
3.400
TBD -335 @
—— -265/26A @
—— -202 @
—— -265/26A @
—— -202 @
HP -
#
u
l
n
49.5/50.5
t
QHS). The data valid window
3.700
t
t
3.350
2.463
t
CK = 10ns
CK = 10ns
CK = 6ns
t
HP (
t
t
CK = 7.5ns
CK = 7.5ns
49/51
t
3.650
CK/2),
2.425
3.300
48.5/52.5
t
DQSQ, and
3.600
2.388
3.250
DERATING DATA VALID WINDOW
48/52
3.550
184-PIN REGISTERED DDR SDRAM DIMM
2.350
3.200
(
Clock Duty Cycle
t
QH -
47.5/53.5
t
16
DQSQ)
3.500
2.313
3.150
24. This limit is actually a nominal value and does
25. To maintain a valid level, the transitioning edge
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
not result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
of the input must:
a) Sustain a constant slew rate from the current
b) Reach at least the target AC level.
c) After the AC target level is reached, continue
be
from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to
each 100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain.
47/53
3.450
AC level through to the target AC level, V
or V
or V
2.275
3.100
to maintain at least the target DC level, V
1V/ns (2V/ns differentially).
IH
IH
(
(
46.5/54.5
AC
DC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3.400
).
).
2.238
3.050
46/54
3.350
2.200
3.000
45.5/55.5
3.300
2.163
2.950
512MB (x72)
t
RFC [MIN]) else
PRELIMINARY
t
45/55
DS and
3.250
2.125
2.900
©2002, Micron Technology, Inc.
IL
t
(
DH for
IL
AC
(
DC
)
)