MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 18

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

NOTES (continued)
38. For slew rates greater than 1V/ns the (LZ)
39. During initialization, V
40. The current Micron part operates below the
41.
42. For the -335, -26A, and -265 modules, I
43. Random addressing changing 50% of data
44. Random addressing changing 100% of data
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
transition will start about 310ps earlier.
equal to or less than V
may be 1.35V maximum during power up, even
if V
42 ohms of series resistance is used between the
V
slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
t
specified to be 35mA.
changing at every transfer.
changing at every transfer.
RAP
TT
DD
supply and the input pin.
/V
t
RCD.
DDQ
are 0 volts, provided a minimum of
DD
DDQ
+ 0.3V. Alternatively, V
, V
TT
, and V
REF
DD
3N is
must be
184-PIN REGISTERED DDR SDRAM DIMM
TT
18
45. CKE must be active (high) during the entire time
46. IDD2N specifies the DQ, DQS, and DM to be
47. Whenever the operating frequency is altered, not
48. Leakage number reflects the worst case leakage
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
t
REF later.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MB (x72)
PRELIMINARY
©2002, Micron Technology, Inc.