MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 10

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
COMMANDS
available commands. For a more detailed description
TRUTH TABLE 1 – COMMANDS
(Note: 1)
TRUTH TABLE 2 – DM OPERATION
(Note: 10)
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select device bank and activate row)
READ (Select device bank and column, and start READ burst)
WRITE (Select device bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in device bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
NAME (FUNCTION)
Write Enable
Write Inhibit
Truth Tables 1 and 2 provide a general reference of
10. Used to mask write data; provided coincident with the corresponding data.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
3. BA0-BA1 provide device bank address and A0-A12 provide row address.
4. BA0-BA1 provide device bank address; A0-A9, 11 provide column address; A10 HIGH enables the auto precharge feature
5. A10 LOW: BA0-BA1 determine which device bank is precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
9. DESELECT and NOP are functionally interchangeable.
= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-code
to be written to the selected mode register.
(nonpersistent), and A10 LOW disables the auto precharge feature.
A10 HIGH: all device banks are precharged and BA0-BA1 are “Don’t Care.”
bursts with auto precharge enabled and for WRITE bursts.
184-PIN REGISTERED DDR SDRAM DIMM
10
of commands and operations, refer to Micron’s 256Mb
DDR SDRAM data sheet.
CS# RAS# CAS# WE#
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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H
X
H
H
L
L
L
L
H
H
H
H
X
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H
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X
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512MB (x72)
Bank/Row
Op-Code
Bank/Col
Bank/Col
PRELIMINARY
ADDR
Code
X
X
X
X
©2002, Micron Technology, Inc.
DM
H
L
NOTES
Valid
6, 7
D Q
X
9
9
3
4
4
8
5
2