MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 7

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

Burst Length
burst oriented, with the burst length being program-
mable, as shown in Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given READ
or WRITE command. Burst lengths of 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Read and write accesses to the DDR SDRAM are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
0*
14
BA1
0*
13
BA0
12
A12 A11
Mode Register Definition
Operating Mode
11
10
A10
M12 M11
0
0
-
9
A9
0
0
-
8
A8
M10
0
0
-
Diagram
7
A7 A6 A5 A4 A3
M9
M6
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
M8 M7
M5
0
1
-
0
0
1
1
0
0
1
1
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
M6-M0
M3
0
1
Valid
Valid
3
-
Burst Length
M2
2
0
0
0
0
1
1
1
1
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
Interleaved
Burst Type
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
184-PIN REGISTERED DDR SDRAM DIMM
2
4
8
7
if a boundary is reached. The block is uniquely se-
lected by A1-A12 when the burst length is set to two, by
A2-A12 when the burst length is set to four and by A3-
A12 when the burst length is set to eight. The remain-
ing address bits are used to select the starting location
within the block. The programmed burst length ap-
plies to both READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition Table.
NOTE: 1. For a burst length of two, A1-A12 select the two-
Length
Burst
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
2
4
8
2. For a burst length of four, A2-A12 select the four-
3. For a burst length of eight, A3-A12 select the
4. Whenever a boundary of the block is reached
Starting Column
data-element block; A0 selects the first access
within the block.
data-element block; A0-A1 select the first access
within the block.
eight-data-element block; A0-A2 select the first
access within the block.
within a given sequence above, the following
access wraps within the block.
A2 A1 A0
0
0
0
0
1
1
1
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Address
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential Type = Interleaved
Table
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
512MB (x72)
PRELIMINARY
©2002, Micron Technology, Inc.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0