MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 6

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

GENERAL DESCRIPTION
namic random-access, 512MB registered memory mod-
ule organized in a x72 (ECC) configuration. This mod-
ule uses internally configured quad-bank DDR
SDRAMs.
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the DDR SDRAM mod-
ule effectively consists of a single 2n-bit wide, one-
clock-cycle data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
ules are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the device bank and row to
be accessed. The address bits registered coincident
with the READ or WRITE command are used to select
the device bank and the starting column location for
the burst access.
mable READ or WRITE burst lengths of 2, 4, or 8 loca-
tions. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at
the end of the burst access.
SDRAM module allows for concurrent operation,
thereby providing high, effective bandwidth by hid-
ing row precharge and activation time.
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
The MT18VDDF6472 is a high-speed CMOS, dy-
The DDR SDRAM module uses a double data rate
A bidirectional data strobe (DQS) is transmitted ex-
The DDR SDRAM module operates from a differen-
Read and write accesses to the DDR SDRAM mod-
The DDR SDRAM module provides for program-
The pipelined, multibank architecture of the DDR
An auto refresh mode is provided, along with a
184-PIN REGISTERED DDR SDRAM DIMM
6
puts are SSTL_2, Class II compatible. For more infor-
mation regarding DDR SDRAM operation, refer to the
Micron 256Mb DDR SDRAM data sheet.
PLL AND REGISTER OPERATION
mode where the control/address input signals are
latched in the register on one rising clock edge and sent
to the DDR SDRAM devices on the following rising clock
edge (data access is delayed by one clock). A phase-lock
loop (PLL) on the module is used to redrive the differen-
tial clock signals CK and CK# to the DDR SDRAM devices
to minimize system clock loading.
SERIAL PRESENCE-DETECT OPERATION
ence-detect (SPD). The SPD function is implemented
using a 2,048-bit EEPROM. This nonvolatile storage de-
vice contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
REGISTER DEFINITION
MODE REGISTER
of operation of the DDR SDRAM. This definition in-
cludes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in the
Mode Register Diagram. The mode register is pro-
grammed via the MODE REGISTER SET command (with
BA0 = 0 and BA1 = 0) and will retain the stored informa-
tion until it is programmed again or the device loses
power (except for bit A8, which is self-clearing).
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in un-
specified operation.
A3 specifies the type of burst (sequential or inter-
leaved), A4-A6 specify the CAS latency, and A7-A12
specify the operating mode.
The DDR SDRAM module is operated in registered
The DDR SDRAM module incorporates serial pres-
The mode register is used to define the specific mode
Reprogramming the mode register will not alter the
Mode register bits A0-A2 specify the burst length,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MB (x72)
PRELIMINARY
©2002, Micron Technology, Inc.