MT18VDDF6472G-202 Micron, MT18VDDF6472G-202 Datasheet - Page 3

• Manufacturer Part Number: MT18VDDF6472G-202
• Description: 184-PIN REGISTERED DDR SDRAM DIMM
• Manufacturer: Micron

PIN DESCRIPTIONS
NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number/symbol information.
64 Meg x72 184 Pin Registered DDR SDRAM DIMM
DDF18C64x72G_A.p65 – Pub. 02/02
27, 29, 32, 37, 41, 43, 48,
115, 118, 122, 125, 130,
PIN NUMBERS
63, 65, 154
137, 138
52, 59
157
141
21
1
WE#, CAS#,
CK0, CK0#
SYMBOL
BA0, BA1
A0-A12
RAS#
CKE0
S0#
V
REF
184-PIN REGISTERED DDR SDRAM DIMM
TYPE
Input
Input
Input
Input
Input
Input
Input
3
Command Inputs: RAS#, CAS#, and WE# (along with
S#) define the command being entered.
Clock: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative
edge of CK#. Output data (DQ and DQS pins) is
referenced to the crossings of CK0 and CK0#.
Clock Enable: CKE HIGH activates and CKE LOW
deactivates the internal clock, input buffers and output
drivers. Taking CKE LOW provides PRECHARGE POWER-
DOWN and SELF REFRESH operations (all device banks
idle), or ACTIVE POWER-DOWN (row ACTIVE in any
device bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout
read and write accesses. Input buffers (excluding CK,
CK# and CKE) are disabled during POWER-DOWN.
Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V
Chip Select: S# enable (registered LOW) and disable
(registered HIGH) the command decoder. All com-
mands are masked when S# is registered HIGH. S0# is
considered part of the command code.
Bank Address: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address Inputs: A0-A12 provide the row address for
ACTIVE commands, and the column address and auto
precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the
respective device bank. A10 sampled during a
PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW,
device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-
code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or
extended mode register) is loaded during the LOAD
MODE REGISTER command.
SSTL_2 reference voltage.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
DD
is applied.
512MB (x72)
PRELIMINARY
©2002, Micron Technology, Inc.