FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 63

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

Sense Drive Status
Sense
information. It has not execution phase and goes
directly to the result phase from the command
phase. Status Register 3 contains the drive status
information.
Specify
The Specify command sets the initial values for
each of the three internal times.
The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode
is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by
the FDRQ pin. Non-DMA mode uses the RQM bit and the interrupt to signal data transfers.
Drive
00
01
02
7F
7F
E
F
0
1
..
..
2M
Status
64
56
60
4
..
63.5
2M
0.5
64
63
1
..
128
112
120
1M
8
..
obtains
500K
256
224
240
Table 27 - Drive Control Delays (ms)
16
..
drive
HUT
128
126
127
1M
1
2
..
The HUT
300K
26.7
426
373
400
..
status
250K
512
448
480
32
..
63
500K
256
252
254
2
4
..
(Head Unload Time) defines the timefrom the end
of the execution phase of one of the read/write
commands to the head unload state. The SRT
(Step Rate Time) defines the time interval between
adjacent step pulses. Note that the spacing
between the first and second step pulses may be
shorter than the remaining step pulses. The HLT
(Head Load Time) defines the time between when
the Head Load signal goes high and the read/write
operation starts. The values change with the data
rate speed selection and are documented in Table
27. The values are the same for MFM and FM.
3.75
0.25
2M
0.5
4
..
HLT
1M
7.5
0.5
8
..
1
300K
426
420
423
3.3
6.7
..
500K
16
15
..
2
1
SRT
300K
26.7
3.33
1.67
25
..
250K
512
504
508
4
8
.
250K
32
30
..
4
2