FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 16
FDC37M81x
Manufacturer Part Number
FDC37M81x
Description
PC98/99 Compliant Enhanced Super I/O Controller
Manufacturer
SMSC Corporation
Datasheet
1.FDC37M81X.pdf
(198 pages)
- Current page: 16 of 198
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STATUS REGISTER A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state of the internal interrupt signal and several disk interface
pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the
PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.
PS/2 Mode
BIT 0 DIRECTION
Active high status indicating the direction of head
movement. A logic "1" indicates inward direction; a
logic "0" indicates outward direction.
BIT 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk
interface input. A logic "0" indicates that the disk is
write protected.
BIT 2 nINDEX
Active low status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface
input. A logic "1" selects side 1 and a logic "0"
selects side 0.
RESET
COND.
PENDING
INT
7
0
nDRV2
6
1
STEP
5
0
16
nTRK0 HDSEL nINDX
N/A
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the STEP output disk
interface output pin.
BIT 6 nDRV2
This function is not supported. This bit is always
read as ‘1’.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy
Disk Interrupt output.
4
3
0
N/A
2
nWP
N/A
1
DIR
0
0
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