FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 193
FDC37M81x
Manufacturer Part Number
FDC37M81x
Description
PC98/99 Compliant Enhanced Super I/O Controller
Manufacturer
SMSC Corporation
Datasheet
1.FDC37M81X.pdf
(198 pages)
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Notes:
1. Receive Pulse Detection Criteria: A received pulse is considered detected if the
2. IRRX:
n IRRX
IRRX
DATA
t1
t1
t1
t1
t1
t1
t1
t2
t2
t2
t2
t2
t2
t2
received pulse is a minimum of 1.41µs.
nIRRX: L5, CRF1 Bit 0 = 0 (default)
Pulse Width at 115kbaud
Pulse Width at 57.6kbaud
Pulse Width at 38.4kbaud
Pulse Width at 19.2kbaud
Pulse Width at 9.6kbaud
Pulse Width at 4.8kbaud
Pulse Width at 2.4kbaud
Bit Time at 115kbaud
Bit Time at 57.6kbaud
Bit Time at 38.4kbaud
Bit Time at 19.2kbaud
Bit Time at 9.6kbaud
Bit Time at 4.8kbaud
Bit Time at 2.4kbaud
L5, CRF1 Bit 0 = 1
0
t2
t1
t2
1
Parameter
FIGURE 21 - IrDA RECEIVE TIMING
t1
0
1
193
0
0
min
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1
3.22
19.5
8.68
17.4
104
208
416
typ
1.6
4.8
9.7
39
78
26
52
1
max
11.07
22.13
44.27
88.55
2.71
3.69
5.53
0
1
units
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
1
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